The present invention relates generally to semiconductor integrated circuits and, more particularly, to structures and methods for programmable low voltage decode circuits with ultra thin tunnel oxides.
Electrically erasable and programmable read only memories (EEPROMs) provide nonvolatile data storage. EEPROM memory cells typically use field-effect transistors (FETs) having an electrically isolated (floating) gate that affects conduction between source and drain regions of the FET. A gate dielectric is interposed between the floating gate and an underlying channel region between source and drain regions. A control gate is provided adjacent to the floating gate, separated therefrom by an intergate dielectric.
In such memory cells, data is represented by charge stored on the polysilicon floating gates. The charge is placed on the floating gate during a write operation using a technique such as hot electron injection or Fowler-Nordheim (FN) tunneling. Fowler-Nordheim tunneling is typically used to remove charge from the polysilicon floating gate during an erase operation. At the present time, FN tunneling is primarily used (see generally, T. P. Ma et al., xe2x80x9cTunneling leakage current in ultrathin ( less than 4 nm) nitride/oxide stack dielectrics,xe2x80x9d IEEE Electron Device Letters, vol. 19, no. 10, pp. 388-390, 1998) as shown in FIG. 1A where the electrons are injected into the conduction band of the oxide by driving the floating gate with a negative potential. Another type of tunneling which has been used is band to band, BTB, tunneling (see generally C. Salm et al., xe2x80x9cGate current and oxide reliability in P+ poly MOS capacitors with poly-Si and Poly-Ge0.3Si0.7 gate material,xe2x80x9d IEEE Electron Device Letters, vol. 19, no. 7, pp. 213-215, July 1998) as shown in FIG. 1B where electrons tunnel out of the valence band, in this case of the silicon substrate, on to the floating gate which is driven to a positive potential.
A flash EEPROM cell has the potential to be smaller and simpler than today""s conventional dynamic random access memory (DRAM) cell. One of the limitations to shrinking a flash EEPROM memory cell has been the requirement for a silicon dioxide gate insulator thickness of approximately 10 nm between the floating polysilicon gate and the silicon substrate forming the channel of a flash field effect transistor. This gate thickness is required to prevent excess charge leakage from the floating gate that would reduce data retention time (targeted at approximately 10 years)
Current n-channel flash memories utilize a floating polysilicon gate over a silicon dioxide gate insulator of thickness of the order 100 xc3x85 or 10 nm in a field effect transistor. (See generally, B. Dipert et al., IEEE Spectrum, pp. 48-52 (Oct. 1993). This results in a very high barrier energy of around 3.2 eV for electrons between the silicon substrate and gate insulator and between the floating polysilicon gate and silicon oxide gate insulator. This combination of barrier height and oxide thickness results in extremely long retention times even at 250 degrees Celsius. (See generally, C. Papadas et al., IEEE Trans, on Electron Devices, 42, 678-681 (1995)). The simple idea would be that retention times are determined by thermal emission over a 3.2 electron volt (eV) energy barrier, however, these would be extremely long so the current model is that retention is limited by F-N tunneling off of the charged gate. This produces a lower xe2x80x9capparentxe2x80x9d activation energy of 1.5 eV which is more likely to be observed. Since the retention time is determined either by thermal excitation of electrons over the barrier or the thermally assisted F-N tunneling of electrons through the oxide, retention times are even longer at room temperature and/or operating temperatures and these memories are for all intensive purposes non-volatile and are also known as non volatile random access memories (NVRAMs). This combination of barrier height and tunnel oxide thickness is not an optimum value in terms of transfer of electrons back and forth between the substrate and floating gate and results in long erase times in flash memories, typically of the order of milliseconds. To compensate for this, a parallel erase operation is performed on a large number of memory cells to effectively reduce the erase time, whence the name xe2x80x9cflashxe2x80x9d or xe2x80x9cflash EEPROMxe2x80x9d originated since this effective erase time is much shorter than the erase time in EEPROMs.
P-channel flash memory cells, having gate oxide thicknesses of approximately 100 xc3x85, have been reported (see generally, T. Ohnakado et al., Digest of Int. Electron Devices Meeting, Dec. 10-13, 1995, Washington D. C., pp. 279-282; T. Ohnakado et al., Digest of Int. Electron Devices Meeting, Dec. 8-11, 1996, San Francisco, pp. 181-184; T. Ohnakado et al., Proc. Symposium on VLSI Technology, Jun. 9-11, 1998), Honolulu, HI, pp. 14-15) and disclosed (see U.S. Pat. No. 5,790,455, issued Aug. 4, 1998, entitled xe2x80x9cLow voltage single supply CMOS electrically erasable read-only memoryxe2x80x9d). These reported and disclosed p-channel flash memory cells work similar to n-channel flash memory cells in that they utilize hot electron effects to write data on to the floating gate. If the magnitude of the drain voltage in a PMOS transistor is higher than the gate voltage, then the electric field near the drain through the gate oxide will be from the gate (most positive) towards the drain (most negative). This can and will cause hot electrons to be injected into the oxide and collected by the floating gate. The mechanisms reported are either channel hot electron injection, CHE, or band-to-band tunneling induced hot electron injection, BTB. The gate current in PMOS transistors (see generally, I. C. Chen et al., IEEE Electron Device Lett., 4:5, 228-230 (1993); and J. Chen et al., Proceedings IEEE Int. SOI Conf. Oct. 1-3, 1991, pp. 8-9) can actually be much higher than the gate current in NMOS transistors (see generally, R. Ghodsi et al., IEEE Electron Device Letters, 19:9, 354-356 (1998)) due to the BTB tunneling. Negatively, higher gate current in the PMOS transistors resulting from this BTB tunneling effect limits the reliability of deep sub-micron CMOS technology, as reported by R. Ghodsi et al. In other words, the reliability of the PMOS array is lowered because of this higher current in the PMOS device.
In co-pending, commonly assigned U.S. patent applications: entitled xe2x80x9cDynamic Flash Memory Cells with UltraThin Tunnel Oxides,xe2x80x9d Ser. No. 09/513,938, filed Feb. 28, 2000, and xe2x80x9cP-Channel Dynamic Flash Memory Cells with UltraThin Tunnel Oxides,xe2x80x9d Ser. No. 09/514,627, filed Feb. 28 ,2000, dynamic memory cells base on floating gates, like those in flash memory cells, over ultrathin tunneling oxides, are disclosed. In these cases write and erase was accomplished by tunneling through the ultrathin gate oxides. The dynamic nature of the cell resulted from using relatively speaking larger potential variations and amounts of charge stored on the floating gates, as a consequence charge could leak on to, or off of, the floating gate by tunneling of carriers to allowed states in the conduction bands of the insulator, FN tunneling, or semiconductor by band to band, BTB, tunneling. The transistors employed there were normal enhancement mode n-channel MOSFETs, or enhancement mode PMOSFETs. However, the dynamic nature of the cells disclosed therein are not suited for the non volatile requirements of decode circuits.
As described above, tunneling has long been used in the erase operation of flash memory devices. Such flash memory devices have further been used in field programmable logic devices such as circuit programmable logic devices, programmable memory address decode and fault-tolerant memory arrays, and embedded functions. However, the use of conventional flash memory devices in such circuit applications suffer the above described drawbacks relating to the speed of the write and erase functions as well as the amount of power consumption.
Thus, there remains a need in the art to develop xe2x80x9cstatic,xe2x80x9d non volatile floating gate transistors, or flash memory cells which can be more successfully implemented in decode circuit applications. Such non volatile floating gate transistors, or flash memory cells should desirably be able to scale down with shrinking design rules and usefully be implemented with ultra thin tunnel gate oxide thicknesses of less than the conventional 100 xc3x85 thick tunnel oxides. That is, it is desirable to develop improved decode circuits which are more responsive, providing faster write and erase times and which can work with much lower voltages than conventional flash memory type devices used in current decode circuit technology. It is further desirable that such decode circuits have a reliability of a number of cycles of performance equivalent or greater than that of current decode circuits using conventional non volatile memory cells and be capable of performing decode operations at a rate comparable to or faster than that of conventional decode circuits.
In the co-filed, co-pending, commonly assigned U.S. patent application: entitled xe2x80x9cStatic NVRAM UltraThin Tunnel Oxides,xe2x80x9d, Ser. No. 09/515,630, filed Feb. 29, 2000 which disclosure is herein incorporated by reference, static non volatile memory cells, NVRAMs, which behave like SRAMs are disclosed.
The present invention describes systems and methods for programmable decode circuits which utilize such a static non volatile memory cell. The programmable depletion mode, p-channel floating gate driver transistors with ultra thin gate oxides will normally work with voltages around one Volt. The decode circuits of the present invention can be programmed with voltages in the range 2.0 to 3.0 Volts. This allows the fabrication of low voltage programmable memory address decode circuits which operate with low voltage power supplies which will be used with CMOS technology which has feature sizes of the order 0.1 xcexcm, 1000 xc3x85, or 100 nm.
The devices are not similar to normal flash memory devices but rather employ a unique device structure and operating conditions to achieve a nonvolatile memory function. There is a range of floating gate potentials over which charge can not leak off of the floating gate since there are no final states to which the electrons can tunnel to in the silicon substrate. In this manner ultrathin gate oxides can be used as to provide a nonvolatile memory function and the transistor in the decode circuit can be programmed to perform different logic functions. Further, the decode circuits of the present invention are well suited to scale with the shrinking design rules of integrated circuit technology.
According to one embodiment of the present invention, an address decoder for a memory device is provided. The address decoder includes a number of address lines and a number of output lines which form an array. A number logic cells are disposed at the intersections of output lines and address lines. Further, a number of non volatile memory cells are disposed at the intersections of the address lines and at least one output line. The number of non volatile memory cells include depletion mode p-channel memory cells. The depletion mode p-channel memory cells have a control gate and a floating gate separated from the control gate by a dielectric layer. According to the teachings of the present invention an oxide layer of less than 50 Angstroms (xc3x85) separates the floating gate from a p-type doped channel region between a source and a drain region in the substrate.
According to another embodiment of the present invention, a method for enabling error correction in a decode circuit which has a number of non volatile, depletion mode p-channel floating gate transistors coupled to a redundant row line is provided. The method includes selectively storing a limited charge on at least one of the floating gates for the number of non volatile depletion mode p-channel floating gate transistors. Selectively storing the limited charge on the at least one of the floating gates controls addressing the redundant row line. The method further includes applying a limited range of floating gate potentials to the number of non volatile, depletion mode p-channel floating gate transistors using a number of address lines. In one embodiment, applying a limited range of floating gate potentials to the number of non volatile, depletion mode p-channel floating gate transistors in the decode circuit includes applying a limited range of floating gate potentials of approximately +/xe2x88x921.0 Volts. One embodiment of this method includes applying a limited range of floating gate potentials using a negative logic system. In one embodiment, the method also includes selectively removing a limited charge on at least one of the floating gates for the number of number of non volatile depletion mode p-channel floating gate transistors. According to the teachings of the present invention, selectively removing the limited charge on the at least one of the floating gates effectively removes that for the number of non volatile depletion mode p-channel floating gate transistors from the decode.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.